Generative adversarial network based scalable on-chip noise sensor placement


The relentless efforts towards power reduction of integrated circuits have led to the prevalence of near-threshold computing paradigms. With the significantly reduced noise margin, therefore, it is no longer possible to fully assure power integrity at design time. As a result, designers seek to contain noise violations, commonly known as voltage emergencies… (More)
DOI: 10.1109/SOCC.2017.8226048

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