Generation of the Optimal Bit-Width Topology of the Fast Hybrid Adder in a Parallel Multiplier

@article{Das2007GenerationOT,
  title={Generation of the Optimal Bit-Width Topology of the Fast Hybrid Adder in a Parallel Multiplier},
  author={Smita Das and Snnil P. Khatri},
  journal={2007 IEEE International Conference on Integrated Circuit Design and Technology},
  year={2007},
  pages={1-6}
}
In state-of-the-art Digital Signal Processing (DSP) and Graphics applications, multiplication is an important and computationally intensive operation, consuming a significant amount of delay. The final carry propagate hybrid adder inside a multiplier plays an important role in determining the performance of the multiplication block. This paper presents an algorithmic approach to generate the optimal bit-width configuration of each of the sub-adders present inside the hybrid adder. Our technique… CONTINUE READING

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