Generation of Primary Input Blocking Pattern for Power Minimization during Scan Testing

@article{Tseng2007GenerationOP,
  title={Generation of Primary Input Blocking Pattern for Power Minimization during Scan Testing},
  author={Wang-Dauh Tseng},
  journal={J. Electronic Testing},
  year={2007},
  volume={23},
  pages={75-84}
}
In this paper we propose a new approach to generate a primary input blocking pattern for applying to the primary inputs during shift cycle such that the switching activity occurred in the combinational part of the circuit under test can be suppressed as much as possible. The primary input blocking technique suppresses transitions of gates in the combinational part during scan by assigning controlling values to one of the gates’ inputs. However, simultaneously assigning controlling values to the… CONTINUE READING