Generating fast logic circuits for m-select n-port Round Robin Arbitration

@article{Ugurdag2013GeneratingFL,
  title={Generating fast logic circuits for m-select n-port Round Robin Arbitration},
  author={H. Fatih Ugurdag and Fatih Temizkan and Sezer G{\"o}ren},
  journal={2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC)},
  year={2013},
  pages={260-265}
}
This paper generalizes the problem of Round Robin Arbitration (RRA) from 1-select to m-select (mRRA) and offers new circuit architectures for it. RRAs are found in networking equipment and computer systems with high throughput buses. We first propose fast/novel circuits for the fundamental problem of finding the first m 1's in an n-bit vector (from the left or right), i.e., generalized m-select Priority Encoder (mPE). The obvious solution to mPE is cascading m regular (1-select) PEs. Our… CONTINUE READING
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