Corpus ID: 16207842

Generating Hardware from Java Using Self-Propagating Flowpaths

@inproceedings{HannaGeneratingHF,
  title={Generating Hardware from Java Using Self-Propagating Flowpaths},
  author={Darrin M. Hanna and Bryant Drew Jones and Lincoln Lorenz and O MarkBowers}
}
microprocessor is adversely affected by the basic fetch-execute cycle. A further performance penalty results from the load-execute-store paradigm associated with the use of local variables in most high-level languages. Implementing a software algorithm directly in hardware such as on an FPGA can alleviate these performance penalties. Such implementations are normally developed in a hardware description language such as VHDL or Verilog. Previous work has been completed to create a compiler for… Expand

Figures and Tables from this paper

Automatic cache partitioning method for high-level synthesis
TLDR
This work presents an automated optimization method for creating custom cache memory architectures for HLS generated designs that combines data reuse savings and memory partitioning to further increase the potential parallelism and alleviate the serialized memory access, increasing performance. Expand
A medium-grained reconfigurable architecture targeting high-level synthesis implementation
  • J. Gorski, D. Hanna
  • Computer Science
  • 2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS)
  • 2017
TLDR
This work presents a medium-grained reconfigurable architecture tailored to implementing HLS generated circuits that achieves a 5.4x reduction in critical path delay compared to a standard FPGA during initial testing. Expand
The FPOA, a Medium-grained Reconfigurable Architecture for High-level Synthesis
TLDR
A novel type of medium-grained reconfigurable architecture that is optimized for a specific circuit structure, namely those generated by HLS, is presented, which gives the FPOA a significant advantage as it can be used across all application domains. Expand
Java bytecode to hardware made easy with bluespec system verilog
TLDR
This paper presents a method for translation of Java bytecode sequences into synthesizable hardware, using the Bluespec System Verilog (BSV) environment, that is intended as an accelerator for existing Java processors, or even standalone hardware. Expand
Flexible Embedded System Design Using Flowpaths
or ASIC. Introduced in this paper is an extension to the flowpaths compiler to allow easier integration of system-components using object-oriented methodologies. System-components can be described byExpand
A comparative study up to 1024 bit Euclid's GCD algorithm FPGA implementation and synthesizing
TLDR
The comparison with previous designs illustrates that the proposed GCD coprocessor design has a throughput efficiency of even two times faster than other designs, which will help the FPGA system designers to better utilize the hardware performance for many applications such as cryptosystems design. Expand
FPGA implementation of variable precision Euclid’s GCD algorithm
TLDR
This paper implements a fast GCD coprocessor based on Euclid's method with variable precisions (32-bit to 1024-bit) and shows that the design area is scalable and can be easily increased or embedded with many other design applications. Expand

References

SHOWING 1-5 OF 5 REFERENCES
Flowpaths: Compiling stack-based IR to hardware
TLDR
A new systems architecture for FPGAs, called flowpaths, is introduced, which can implement Java bytecodes or software programs written in Forth directly in an FPGA without the need for a microprocessor core. Expand
Executing large algorithms on low-capacity FPGAs using flowpath partitioning and runtime reconfiguration
TLDR
A new method of executing a software program on an FPGA for embedded systems using a new technique to compile Java programs directly to special-purpose processors that are called ''flowpaths''. Expand
Flexible Embedded System Design Using Flowpaths
or ASIC. Introduced in this paper is an extension to the flowpaths compiler to allow easier integration of system-components using object-oriented methodologies. System-components can be described byExpand
A Compiler to Generate Hardware from Java Byte Codes for High Performance, Low Energy Embedded Systems
Improved valves for use within medical devices include a valve body having a plurality of fluid-passing openings, a resilient liner having raised portions defining flow paths, and a plug having aExpand
JStamp: Real-time Native Java Module
  • JStamp: Real-time Native Java Module
  • 2003