# Generalized Water-Filling for Source-Aware Energy-Efficient SRAMs

@article{Kim2018GeneralizedWF,
title={Generalized Water-Filling for Source-Aware Energy-Efficient SRAMs},
author={Yongjune Kim and Mingu Kang and Lav R. Varshney and Naresh R Shanbhag},
journal={IEEE Transactions on Communications},
year={2018},
volume={66},
pages={4826-4841}
}
• Published 19 October 2017
• Computer Science
• IEEE Transactions on Communications
Conventional low-power static random access memories (SRAMs) reduce read energy by decreasing the bit-line voltage swings uniformly across the bit-line columns. This is because the read energy is proportional to the bit-line swings. On the other hand, bit-line swings are limited by the need to avoid decision errors especially in the most significant bits. We propose a principled approach to determine optimal non-uniform bit-line swings by formulating convex optimization problems. For a given…

## Figures and Tables from this paper

### SRAM Bit-line Swings Optimization using Generalized Waterfilling

• Computer Science
2018 IEEE International Symposium on Information Theory (ISIT)
• 2018
Numerical results show that energy-optimal swing assignment reduces energy consumption by half at a peak signal-to-noise ratio of 30dB for an 8-bit accessed word.

### On the Optimal Refresh Power Allocation for Energy-Efficient Memories

• Computer Science
2019 IEEE Global Communications Conference (GLOBECOM)
• 2019
A principled approach to optimizing the refresh power allocation is proposed and a convex optimization problem to minimize the word mean squared error for a refresh power constraint is formulated to guarantee the optimality of the obtained refresh power allocations.

### Optimizing Write Fidelity of MRAMs via Iterative Water-filling Algorithm

• Computer Science
ArXiv
• 2021
The numerical results show that the optimized write pulses can achieve 40% write energy reduction for a given classiﬁcation accuracy, and it is proved that the proposed algorithm can reduce the MSE exponentially with the number of bits per word.

### Optimizing Write Fidelity of MRAMs by Alternating Water-Filling Algorithm

• Computer Science
IEEE Transactions on Communications
• 2022
A biconvex optimization problem to optimize write fidelity given energy and latency constraints is formulated and it is proved that the algorithm can reduce the MSE exponentially with the number of bits per word.

### Optimizing the Write Fidelity of MRAMs

• Computer Science
2020 IEEE International Symposium on Information Theory (ISIT)
• 2020
This paper considers the mean squared error (MSE) as a fidelity metric and proposes an iterative water-filling algorithm to minimize the MSE, and formulate an optimization problem to maximize the memory fidelity given energy constraints.

### The Deep In-Memory Architecture (DIMA)

• Computer Science
• 2020
This chapter describes the Deep In-memory Architecture (DIMA) by first showing how the algorithmic data-flow of commonly used ML algorithms is well-matched to DIMA’s intrinsic architectural data- flow, and in spite of being intrinsically analog.

### Deep In-Memory Architectures for Machine Learning–Accuracy Versus Efficiency Trade-Offs

• Computer Science
IEEE Transactions on Circuits and Systems I: Regular Papers
• 2020
This paper establishes models and methods to understand the fundamental energy-delay and accuracy trade-offs underlying DIMA by presenting silicon-validated energy, delay, and accuracy models and employing these to quantify D IMA’s decision-level accuracy and to identify the most effective design parameters to maximize its EDP gains at a given level of accuracy.

### Shannon-Inspired Statistical Computing for the Nanoscale Era

• Computer Science
Proceedings of the IEEE
• 2019
A Shannon-inspired statistical model of computation (statistical computing) that addresses the statistical attributes of both emerging cognitive workloads and nanoscale fabrics within a common framework for the design of computing systems that approach the limits of energy efficiency, latency, and accuracy.

### Optimizing the Energy Efficiency of Unreliable Memories for Quantized Kalman Filtering

• Engineering, Computer Science
Sensors
• 2022
An error propagation model is developed that accurately predicts the covariance of the estimation error and gives a relation between the performance of the filter and its energy consumption, depending on the noise level in the memories.

### Improving the Energy-Efficiency of a Kalman Filter Using Unreliable Memories

• Engineering
ICASSP 2021 - 2021 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)
• 2021
A method is proposed to optimize the bit energy allocation in the memory, and it is shown from numerical simulations that this method allows for important energy gains.

## References

SHOWING 1-10 OF 55 REFERENCES

### Approximate SRAMs With Dynamic Energy-Quality Management

• Engineering
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
• 2016
This analysis investigates variation-resilient techniques that enable dynamic management of the energy-quality tradeoff down to the bit level and shows that the joint adoption of multiple bit-level techniques provides substantially larger energy gains than individual techniques.

### Heterogeneous SRAM Cell Sizing for Low-Power H.264 Applications

• Computer Science, Engineering
IEEE Transactions on Circuits and Systems I: Regular Papers
• 2012
A heterogeneous SRAM sizing approach for the embedded memory of H.264 video processor, where the more important higher order data bits are stored in the relatively larger SRAM bit-cells and the less important bits are stores in the smaller ones, which allows the better video quality even in lower voltage operation.

### SRAM for Error-Tolerant Applications With Dynamic Energy-Quality Management in 28 nm CMOS

• Engineering
IEEE Journal of Solid-State Circuits
• 2015
A voltage-scaled SRAM for both error-free and error-tolerant applications is presented that dynamically manages the energy/quality trade-off based on application need and two variation-resilient techniques are selectively applied to bit positions having larger impact on the overall quality.

### Nanometer Variation-Tolerant SRAM: Circuits and Statistical Design for Yield

• Engineering
• 2012
Variability is one of the most challenging obstacles for IC design in the nanometer regime. In nanometer technologies, SRAM show an increased sensitivity to process variations due to low-voltage

### A Priority-Based 6T/8T Hybrid SRAM Architecture for Aggressive Voltage Scaling in Video Applications

• Computer Science
IEEE Transactions on Circuits and Systems for Video Technology
• 2011
We present a voltage-scalable and process-variation resilient, hybrid memory architecture, suitable for use in MPEG-4 video processors such that power dissipation can be traded for graceful

### Application-Specific SRAM Design Using Output Prediction to Reduce Bit-Line Switching Activity and Statistically Gated Sense Amplifiers for Up to 1.9$\times$ Lower Energy/Access

• Engineering
IEEE Journal of Solid-State Circuits
• 2014
A prediction-based reduced bit-line switching activity scheme is proposed to reduce switching activity on the bit-lines based on the proposed bit-cell and array structure and a statistically gated sense-amplifier approach is used to exploit signal statistics on thebit-lines to reduce energy consumption of the sensing network.

### Maximum-information storage system: Concept, implementation and application

• Xin Li
• Computer Science, Engineering
2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
• 2010
This paper proposes a new SRAM design methodology that is referred to as maximum-information storage system (MISS), which aims to maximize the information density (i.e., the number of information bits per unit area).

### Unequal-error-protection codes in SRAMs for mobile multimedia applications

• Computer Science
2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
• 2011
A novel metric, word mean squared error, is used, to measure the reliability of a SRAM word when different bits are not equally significant, and an optimization algorithm based on dynamic programming is constructed to construct the UEPECC that assigns different protection levels to bits according to their significance.

### Characterization of SRAM sense amplifier input offset for yield prediction in 28nm CMOS

• Engineering
2011 IEEE Custom Integrated Circuits Conference (CICC)
• 2011
A process control monitor for SRAM SA offset is proposed and implemented in 28nm LP CMOS technology, which provides accurate measurement of SA offset from a large sample size and accounts for all proximity effects that may affect the SA offset.

### Priority Based Error Correction Code (ECC) for the Embedded SRAM Memories in H.264 System

• Engineering, Computer Science
J. Signal Process. Syst.
• 2013
A priority based ECC (PB-ECC) approach, where the more important higher order bits are protected with higher priority than the less important lower order bits since the human visual system is less sensitive to LOB errors is presented.