Gate sizing for crosstalk reduction under timing constraints by Lagrangian relaxation

@article{Sinha2004GateSF,
  title={Gate sizing for crosstalk reduction under timing constraints by Lagrangian relaxation},
  author={Debjit Sinha and Hai Zhou},
  journal={IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.},
  year={2004},
  pages={14-19}
}
This work presents a post-route, timing-constrained gate-sizing algorithm for crosstalk reduction. Gate-sizing has emerged as a practical and feasible method to reduce crosstalk in deep sub-micron VLSI circuits. It is however critical to ensure that the timing constraints of the circuit are not violated after sizing. We present an iterative gate-sizing algorithm for crosstalk reduction based on Lagrangian relaxation that optimizes area and power while ensuring that the given timing constraints… CONTINUE READING
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