Gate sizing for constrained delay/power/area optimization

  title={Gate sizing for constrained delay/power/area optimization},
  author={Olivier Coudert},
  journal={IEEE Trans. VLSI Syst.},
Gate sizing has a significant impact on the delay, power dissipation, and area of the final circuit. It consists of choosing for each node of a mapped circuit a gate implementation in the library so that a cost function is optimized under some constraints. For instance, one wants to minimize the power consumption and/or the area of a circuit under some user-defined delay constraints, or to obtain the fastest circuit within a given power budget. Although this technology-dependent optimization… CONTINUE READING
Highly Cited
This paper has 119 citations. REVIEW CITATIONS
89 Citations
28 References
Similar Papers


Publications citing this paper.
Showing 1-10 of 89 extracted citations

120 Citations

Citations per Year
Semantic Scholar estimates that this publication has 120 citations based on the available data.

See our FAQ for additional information.


Publications referenced by this paper.
Showing 1-10 of 28 references

TILOS: A posynomial programming approach to transistor sizing,

  • J. P. Fishburn, A. E. Dunlop
  • inProc. ICCAD’85,
  • 1985
Highly Influential
5 Excerpts

Delay analysis of seriesconnected MOSFET circuits

  • A. R. Newton
  • Proc . 14 th DAC , June
  • 1997

An accurate slopedependent delay model

  • U. Barkai, J. Ben-Simon
  • Proc . 31 st DAC , June
  • 1994

Logic Synthesis

  • S. Devadas, A. Ghosh, K. Keutzer
  • New York: McGraw-Hill
  • 1994

Similar Papers

Loading similar papers…