Gate level static power estimation in UDSM processes

@article{AlHertani2008GateLS,
  title={Gate level static power estimation in UDSM processes},
  author={H. Al-Hertani and Dhamin Al-Khalili and C. Rozon},
  journal={2008 International Conference on Microelectronics},
  year={2008},
  pages={212-215}
}
This paper introduces a new approach to estimating static leakage current, which leads to the calculation of static power dissipation in basic and complex logic gates. The approach utilizes a transistor collapsing scheme which merges pull-up/down networks into transistor stacks. Leakage current in these stacks can then be easily estimated using a stack estimator proposed by Hertani, et al.. The proposed approach is highly analytical (at the logic gate level), therefore exhibiting high… CONTINUE READING

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