Gate-length biasing for runtime-leakage control

  title={Gate-length biasing for runtime-leakage control},
  author={Puneet Gupta and Andrew B. Kahng and Puneet Sharma and Dennis Sylvester},
  journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
Leakage power has become one of the most critical design concerns for the system level chip designer. While lowered supplies (and consequently, lowered threshold voltage) and aggressive clock gating can achieve dynamic power reduction, these techniques increase the leakage power and, therefore, causes its share of total power to increase. Manufacturers face the additional challenge of leakage variability: Recent data indicate that the leakage of microprocessor chips from a single 180-nm wafer… CONTINUE READING
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