Gate-induced fermi level tuning in InP nanowires at efficiency close to the thermal limit.

Abstract

As downscaling of semiconductor devices continues, one or a few randomly placed dopants may dominate the characteristics. Furthermore, due to the large surface-to-volume ratio of one-dimensional devices, the position of the Fermi level is often determined primarily by surface pinning, regardless of doping level. In this work, we investigate the possibility… (More)
DOI: 10.1021/nl104032s

3 Figures and Tables

Topics

  • Presentations referencing similar topics