Gate-Level Design Exploiting Dual Supply Voltages for Power-Driven Applications

@inproceedings{Yeh1999GateLevelDE,
  title={Gate-Level Design Exploiting Dual Supply Voltages for Power-Driven Applications},
  author={Chingwei Yeh and Min-Cheng Chang and Shih-Chieh Chang and Wen-Ben Jone},
  booktitle={DAC},
  year={1999}
}
The advent of portable and high-density devices has made power consumption a critical design concern. In this paper, we address the problem of reducing power consumption via gate-level voltage scaling for those designs that are not under the strictest timing budget. We first use a maximum-weighted independent set formulation for voltage reduction on non-critical parts of the circuit. Then, we use a minimum-weighted separator set formulation to do gate sizing and integrate the sizing procedure… CONTINUE READING

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Key Quantitative Results

  • An average of 19.12% power reduction over the circuits having only one supply voltage has been achieved.
  • and an average of 19.12% power reduction over the circuits having only one supply voltage has been achieved.
  • and an average of 19.12% power reduction over the circuits having only one supply voltage has been achieved.
  • We showed that integrating voltage scaling with gate sizing produces an aver­age of 19.12% power reduction over the circuits that have only one supply voltage.

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Technology Mapping and Clustering for FPGA Architectures With Dual Supply Voltages

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Noise-aware multiple-voltage assignment for gate-level power optimization

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