GRAAL: a new fault tolerant design paradigm for mitigating the flaws of deep nanometric technologies

@article{Nicolaidis2007GRAALAN,
  title={GRAAL: a new fault tolerant design paradigm for mitigating the flaws of deep nanometric technologies},
  author={Michael Nicolaidis},
  journal={2007 IEEE International Test Conference},
  year={2007},
  pages={1-10}
}
Silicon-based CMOS technologies are fast approaching their ultimate limits. By approaching these limits, power dissipation, fabrication yield, and reliability worsen steadily making further nanometric scaling increasingly difficult. These problems would stop further scaling of silicon-based CMOS technologies at channel lengths between 10 and 20 nm. But even… CONTINUE READING

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