GORDIAN: VLSI placement by quadratic programming and slicing optimization

  title={GORDIAN: VLSI placement by quadratic programming and slicing optimization},
  author={J{\"u}rgen M. Kleinhans and Georg Sigl and Frank M. Johannes and Kurt Antreich},
  journal={IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.},
The authors present a placement method for cell-based layout styles. [] Key Method In contrast, GORDIAN maintains the simultaneous treatment of all cells over all global optimization steps, thereby considering constraints that reflect the current dissection of the circuit. The global optimizations are performed by solving quadratic programming problems that possess unique global minima. Improved partitioning schemes for the stepwise refinement of the placement are introduced.

Faster and better global placement by a new transportation algorithm

BonnPlace is a new VLSI placement algorithm that combines the advantages of analytical and partitioning-based placers and can improve the results of leading-edge placement tools by about 5%.

Parallel algorithms for slicing based final placement

  • Henning SpruthG. Sigl
  • Computer Science
    Proceedings EURO-DAC '92: European Design Automation Conference
  • 1992
The authors present parallel algorithms for solving the final placement problem of rectangular modules assuming predefined neighborhood relations, between the modules to be placed, by enumerating all arrangements of local module subsets and proposing new algorithms for the enumeration on message-passing parallel computers.

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Linear decomposition algorithm for VLSI design applications

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RITUAL: a performance driven placement algorithm

An algorithm for obtaining a placement of large scale cell-based ICs subject to performance constraints, formulated as a constrained programming problem and solved in two phases: continuous and discrete.

Congestion Minimization in Modern Placement Circuits

This chapter proposes a placement tool called Dragon which deploys hierarchical techniques to place large-scale mixed size designs that may contain thousand of macro blocks and millions of standard cells and effectively produce legal final layouts with a short runtime.

Quadratic 0/1 optimization and a decomposition approach for the placement of electronic circuits

A decomposition approach to the placement problem is presented and results above NP-hardness and the existence ofε-approximative algorithms for the involved optimization problems are given.



GORDIAN: a new global optimization/rectangle dissection method for cell placement

A placement method for cell-based layout styles composed of alternating and interacting global optimization and partitioning phases is presented, which maintains the simultaneous treatment of all cells during optimization over all levels of partitioning.

Module Placement Based on Resistive Network Optimization

  • Chung-Kuan ChengE. Kuh
  • Computer Science
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  • 1984
A new constructive placement and partitioning method based on resistive network optimization is proposed, which is efficient because it takes advantage of net-list sparsity and has a complexity of O[n1.4 log n].

Near-Optimal Placement Using a Quadratic Objective Function

  • J. Blanks
  • Computer Science
    22nd ACM/IEEE Design Automation Conference
  • 1985
Experiments show that with the quadratic metric used in this study, at least for homogenous interchangeable devices confined to a square grid, pairwise interchange suffices to move the placement very close to the global optimum over a range of 100 to 1600 devices.

Mason: A Global Floorplanning Approach for VLSI Design

A global floorplanning approach is presented which allows designers to quickly explore layout issues during the initial stages of the IC design process. The approach is based on a combined mincut and

Optimal slicing of plane point placements

An algorithm for finding an optimal floor plan among all slicing structures consistent with a given plane point placement is presented and is proven to be of polynomial time complexity in case all shape constraints are integer stair case functions.

A Min-Cut Placement Algorithm for General Cell Assemblies Based on a Graph Representation

  • U. Lauther
  • Computer Science
    16th Design Automation Conference
  • 1979
A new placement algorithm for general cell assemblies is presented which combines the ideas of polar graph representation and min-cut placement and the various methods for placement improvement and global routing.

Proud: a fast sea-of-gates placement algorithm

We present a fast and effective placement algorithm which takes advantage of inherent scarcity in the connectivity specification. It solves repeatedly sparse linear equations by the SOR (Successive

A Procedure for Placement of Standard-Cell VLSI Circuits

  • A. DunlopB. Kernighan
  • Computer Science
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  • 1985
A method of automatic placement for standard cells (polycells) that yields areas within 10-20 percent of careful hand placements is described, based on graph partitioning to identify groups of modules that ought to be close to each other.

A Linear-Time Heuristic for Improving Network Partitions

An iterative mincut heuristic for partitioning networks is presented whose worst case computation time, per pass, grows linearly with the size of the network. In practice, only a very small number of