GF(2^m) Multiplication and Division Over the Dual Basis

@article{Fenn1996GF2mMA,
  title={GF(2^m) Multiplication and Division Over the Dual Basis},
  author={S.T.J. Fenn and Mohammed Benaissa and David Taylor},
  journal={IEEE Trans. Computers},
  year={1996},
  volume={45},
  pages={319-327}
}
In this paper an algorithm for GF(2/sup m/) multiplication/division is presented and a new, more generalized definition of duality is proposed. From these the bit-serial Berlekamp multiplier is derived and shown to be a specific case of a more general class of multipliers. Furthermore, it is shown that hardware efficient, bit-parallel dual basis multipliers can also be designed. These multipliers have a regular structure, are easily extended to different GF(2/sup m/) and hence suitable for VLSI… 
View via Publisher
ee.iitm.ac.in
142 Citations
Highly Influential Citations
9
Background Citations
33
Methods Citations
13
Results Citations
3

Figures and Tables from this paper

142 Citations

Bit-parallel finite field multipliers for irreducible trinomials

The most important new result is the reduction, in two of the five studied trinomials, of the time complexity with respect to the best known results.

Dual basis digit serial GF(2 m ) multiplier

A new digit serial GF(2 m ) multiplier based on the dual basis representation is presented for the first time in this paper, and has low latency, and its digit size is not restricted by the type of primitive polynomial being used.

Low complexity bit-parallel polynomial basis multipliers over binary fields for special irreducible pentanomials

A Novel Digit-Serial Dual Basis Systolic Karatsuba Multiplier over GF(2(superscript m))

This study presents a novel digit-serial dual basis multiplier that is different from existing ones with a modified cut-set method using Karatsuba algorithm, which saves 54% space complexity and 30% time complexity as compared to existing similar studies with NIST suggested values for elliptic curve cryptosystem.

A digit-serial multiplier for finite field GF(2m)

Analysis shows that the computational delay time of the proposed architecture is significantly less than the previously proposed digit-serial systolic multiplier, and since the new architecture has the features of regularity, modularity, and unidirectional data flow, it is well suited to VLSI implementation.

Efficient Reconfigurable Implementation of Canonical and Normal Basis Multipliers Over Galois Fields GF(2m) Generated by AOPs

A new method for multiplication in the canonical and normal basis over GF(2m) generated by an AOP (all-one-polynomial), which is named the transpositional method, is presented, based on the grouping and sharing of subexpressions.

Efficient Multiplier Architectures for Galois Fields GF(2 4n)

A new class of multipliers for finite fields GF((2/sup n/)/sup 4/) is introduced, based on a modified version of the Karatsuba-Ofman algorithm, which leads to architectures which show a considerably improved gate complexity compared to traditional approaches and reduced delay if compared with KOA-based architectures with separate module reduction.

New Bit-Parallel Systolic Architectures for Computing Multiplication, Multiplicative Inversion and Division in GF(2m) Under Polynomial Basis and Normal Basis Representations

A new bit-parallel systolic multiplier over GF(2m) under the polynomial basis and normal basis is proposed, well suited to VLSI systems due to their regular interconnection pattern and modular structure.

High-Throughput Low-Complexity Unified Multipliers Over $GF(2^{m})$ in Dual and Triangular Bases

A high-throughput low-complexity unified multiplier for triangular and dual bases is presented, and is referred to as basic architecture, and enjoys slightly simpler and more regular structure due to use of the mentioned bases.

High-Speed Polynomial Basis Multipliers Over $GF(2^{m})$ for Special Pentanomials

  • J. Imaña
  • Mathematics, Computer Science
    IEEE Transactions on Circuits and Systems I: Regular Papers
  • 2016
The multiplier here presented has the lowest time complexity known to date for similar multipliers based on this type of irreducible pentanomials.
...

References

SHOWING 1-10 OF 27 REFERENCES

A Fast VLSI Multiplier for GF(2m)

A new algorithm for performing fast multiplication in GF(2^{m} ), which is O(m) in computation time and implementation area is presented and the bit-slice architecture of a serial-in-serial-out modulo multiplier is described.

VLSI Architectures for Computing Multiplications and Inverses in GF(2m)

The designs developed for the Massey-Omura multiplier and the computation of inverse elements are regular, simple, expandable, and therefore, naturally suitable for VLSI implementation.

Bit-Serial Systolic Divider and Multiplier for Finite Fields GF(2^m)

A systolic structure for bit-serial division over the field GF(2/sup m/) is developed to avoid global data communications and dependency of the time step duration on m, important for applications where the value of m is large.

Division and bit-serial multiplication over GF(qm)

Division and bit-serial multiplication in finite fields are considered. Using co-ordinates of the supporting elements it is shown that, when field elements are represented by polynomials, division…

SIGMA: a VLSI systolic array implementation of a Galois field GF(2 m) based multiplication and division algorithm

A new algorithm based on a pattern matching technique for computing multiplication and division in GF(2/sup m/) is presented and an efficient systolic architecture is described for implementing the algorithm which can produce a new result every clock cycle and the multiplication anddivision operations can be interleaved.

A Comparison of VLSI Architecture of Finite Field Multipliers Using Dual, Normal, or Standard Bases

Three different finite-field multipliers are presented: (1) a dual-basis multiplier due to E.R. Berlekamp (1982); the Massey-Omura normal basis multiplier; and (3) the Scott-Tavares-Peppard standard…

Improved algorithm for division over GF(2m)

An improved algorithm based on a look-ahead procedure that allows division over GF(2/Sup m/) to be performed in any number of clock cycles up to 2/sup m/-1 is proposed and used in solving the key equation for single-error correcting Reed-Solomon codes.

The VLSI Implementation of a Reed—Solomon Encoder Using Berlekamp's Bit-Serial Multiplier Algorithm

It is shown in this paper that the new dual-basis RS encoder can be realized readily on a single VLSI chip with NMOS technology.

A VLSI Architecture for Fast Inversion in GF(2^m)

  • G. Feng
  • Computer Science
    IEEE Trans. Computers
  • 1989
A new algorithm for performing fast inversion in GF (2/sup m/) is presented, using serial-in-parallel-out multiplication, which is highly regular, modular, and well suited for VLSI implementation.

Bit-serial Reed - Solomon encoders

  • E. Berlekamp
  • Computer Science
    IEEE Transactions on Information Theory
  • 1982
New concepts and techniques for implementing encoders for Reed-Solomon codes, with or without interleaving are presented, including only fields of order 2”, where m m ight be any integer.