GEN03-6: Investigation of Error Floors of Structured Low-Density Parity-Check Codes by Hardware Emulation

@article{Zhang2006GEN036IO,
  title={GEN03-6: Investigation of Error Floors of Structured Low-Density Parity-Check Codes by Hardware Emulation},
  author={Zhengya Zhang and Lara Dolecek and Borivoje Nikolic and Venkat Anantharam and Martin J. Wainwright},
  journal={IEEE Globecom 2006},
  year={2006},
  pages={1-6}
}
Several high performance LDPC codes have parity-check matrices composed of permutation submatrices. We design a parallel-serial architecture to map the decoder of any structured LDPC code in this large family to a hardware emulation platform. A peak throughput of 240 Mb/s is achieved in decoding the (2048,1723) Reed-Solomon based LDPC (RS-LDPC) code. Experiments in the low bit error rate (BER) region provide statistics of the error traces, which are used to investigate the causes of the error… CONTINUE READING
Highly Cited
This paper has 80 citations. REVIEW CITATIONS
52 Citations
12 References
Similar Papers

Citations

Publications citing this paper.
Showing 1-10 of 52 extracted citations

80 Citations

051015'08'11'14'17
Citations per Year
Semantic Scholar estimates that this publication has 80 citations based on the available data.

See our FAQ for additional information.

References

Publications referenced by this paper.
Showing 1-10 of 12 references

Code construction and FGPA implementation of capacity approaching low error-floor LDPC decoder

  • L. Yang, H. Liu, R. Shi
  • to appear in IEEE Trans. on Circuits and Systems…
  • 2006
1 Excerpt

Array codes as low-density parity check codes

  • J. Fan
  • Proc. 2 Int. Symp. Turbo Codes and Related Topics…
  • 2000
1 Excerpt

Similar Papers

Loading similar papers…