Functionally Testable Path Delay Faults on a Microprocessor

  title={Functionally Testable Path Delay Faults on a Microprocessor},
  author={Wei-Cheng Lai and Angela Krstic and Kwang-Ting Cheng},
  journal={IEEE Design & Test of Computers},
gy are integrating more logic into chips while chips are operating at higher speeds. Ensuring that designs meet performance specifications requires application of delay tests. A problem of delay-testing microprocessors is that on-chip clock speed increases dramatically while the tester’s speed does not. This trend implies an increasing yield loss due to external testing since guardbanding to cover tester errors results in loss of more and more good chips. One way to resolve this problem is… CONTINUE READING
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Publications referenced by this paper.
Showing 1-10 of 10 references

Classification and identification of nonrobust untestable path delay faults

IEEE Trans. on CAD of Integrated Circuits and Systems • 1996
View 3 Excerpts

U . Sparmann et al . , “ Fast Identification of Robust Dependent Path Delay Faults Classification and Identification of Nonrobust Untestable Path Delay Faults

S. T. Chakradhar Krstic
IEEE Trans . on Computer - Aided Design of Integrated Circuits and Systems • 1996

VLSI Design Course: VHDL-Modeling and Synthesis of the DLXS

M. Gumm
RISC Processor, • 1995

On Delay Fault Testing in Logic Circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems • 1987