Place and route for massively parallel hardware-accelerated functional verification
verification of the z990 superscalar, multibook microprocessor complex D. G. Bair S. M. German W. D. Wollyung E. J. Kaminski, Jr. J. Schafer M. P. Mullen W. J. Lewis R. Wisniewski J. Walter S. Mittermaier V. Vokhshoori R. J. Adkins M. Halas T. Ruane U. Hahn This paper describes the verification methods and techniques that were established to verify the microarchitecture and architectural correctness of the z990 microprocessor and storage subsystem. The ring-based, four-book storage subsystem links 64 superscalar microprocessors together in this system. The verification process started at the unit level, which focused on the correctness of the microarchitecture, and then proceeded to the element level to verify the architectural correctness of the microprocessor and storage subsystem. After successfully completing element stress testing, the components were combined and verified at the system level. Since the methods used at system-level verification were much the same as the ones used on the CMOS-based IBM S/390 Parallel Enterprise Server G4, the focus of this paper is on the work done at the unit and element levels.