Functional verification of complete sequential behaviors: A formal treatment of discrepancies between system-level and RTL descriptions

Abstract

Formal techniques allow exhaustive verification on circuit design (at least in theory), but due to actual computational limitations, workarounds must always be adopted to check only a portion of the design at a time. Sequential equivalence checking is an effective approach, but it can only be applied between circuit descriptions where a one-to-one… (More)
DOI: 10.1109/IDT.2013.6727074

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