Functional Fault Equivalence and Diagnostic Test Generation in Combinational Logic Circuits Using Conventional ATPG

@article{Veneris2005FunctionalFE,
  title={Functional Fault Equivalence and Diagnostic Test Generation in Combinational Logic Circuits Using Conventional ATPG},
  author={Andreas G. Veneris and Robert Chang and Magdy S. Abadir and Sep Seyedi},
  journal={J. Electronic Testing},
  year={2005},
  volume={21},
  pages={495-502}
}
Fault equivalence is an essential concept in digital design with significance in fault diagnosis, diagnostic test generation, testability analysis and logic synthesis. In this paper, an efficient algorithm to check whether two faults are equivalent is presented. If they are not equivalent, the algorithm returns a test vector that distinguishes them. The proposed approach is complete since for every pair of faults it either proves equivalence or it returns a distinguishing vector. The advantage… CONTINUE READING
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