Fully integrated 54nm STT-RAM with the smallest bit cell dimension for high density memory application

@article{Chung2010FullyI5,
  title={Fully integrated 54nm STT-RAM with the smallest bit cell dimension for high density memory application},
  author={Suock Chung and K.-M. Rho and S.-D. Kim and H.-J. Suh and D.-J. Kim and H.-J. Kim and S.-H. Lee and J.-H. Park and H.-M. Hwang and S.-M. Hwang and J.-Y. Lee and Y.-B. An and J.-U. Yi and Y.-H. Seo and D.-H. Jung and M.-S. Lee and S Cho and J.-N. Kim and G.-J. Park and Gyuan Jin and Alexander Driskill-Smith and Valeriy M Nikitin and Adrian A Ong and Xueti Tang and Yongki Brave Kim and J.-S. Rho and S.-K. Park and S.-W. Chung and J.-G. Jeong and S.-J. Hong},
  journal={2010 International Electron Devices Meeting},
  year={2010},
  pages={12.7.1-12.7.4}
}
A compact STT(Spin-Transfer Torque)-RAM with a 14F2 cell was integrated using modified DRAM processes at the 54nm technology node. The basic switching performance (R-H and R-V) of the MTJs and current drivability of the access transistors were characterized at the single bit cell level. Through the direct access capability and normal chip operation in our STT-RAM test blocks, the switching behavior of bit cell arrays was also analyzed statistically. From this data and from the scaling trend of… CONTINUE READING
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