Fully Robust Path Delay Fault Testability using KEP-SOP


Full testability is a desirable property network and maintaining the testability of multi-level logic synthesis is very complicated. In our paper propose new technique which maintains fully testable circuit with function mode under the robust path delay fault model. The preservation of testability of these networks under the stuck-at-fault model and Path delay model, preservation of testability the K-EPSOP is typical but it we proposed robust path delay fault model using

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@inproceedings{Sinsinwar2011FullyRP, title={Fully Robust Path Delay Fault Testability using KEP-SOP}, author={Gayaprasad Sinsinwar and Abhishek Acharya and Ellen Sentovich and Kulbir Singh and Lucian0 Lavagno and Chang-Joo Moon and A. S. R. Murgai and Hamid Savoj and Philipp Stephan and Robert K. Brayton and Junhao Shi and G{\"{o}rschwin Fey and Rolf Drechsler and Rolf Drechsler”BDD and K -EPSOP}, year={2011} }