Fully Depleted Ge CMOS Devices and Logic Circuits on Si

@article{Wu2016FullyDG,
  title={Fully Depleted Ge CMOS Devices and Logic Circuits on Si},
  author={Heng Wu and P. Ye},
  journal={IEEE Transactions on Electron Devices},
  year={2016},
  volume={63},
  pages={3028-3035}
}
  • Heng Wu, P. Ye
  • Published 2016
  • Materials Science
  • IEEE Transactions on Electron Devices
We systematically studied Ge CMOS devices and logic circuits fabricated on a GeOI substrate, with the novel recessed channel and source/drain structures. Various channel lengths (Lch) from 500 to 30 nm and channel thicknesses (Tch) from 90 to 10 nm are implemented into the Ge CMOS devices and comprehensive geometry dependence analysis is carried out in terms of both Lch and Tch. With shrinking Tch, the gate electrostatics are enhanced significantly but the on-state performance is found to be… Expand
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