Full-wave PEEC time-domain method for the modeling of on-chipinterconnects

@article{Restle2001FullwavePT,
  title={Full-wave PEEC time-domain method for the modeling of on-chipinterconnects},
  author={Phillip Restle and Albert E. Ruehli and Steven G. Walker and George Papadopoulos},
  journal={IEEE Trans. on CAD of Integrated Circuits and Systems},
  year={2001},
  volume={20},
  pages={877-886}
}
With the advances in the speed of high-performance chips, inductance effects in some on-chip interconnects have become significant. Specific networks such as clock distributions and other highly optimized circuits are especially impacted by inductance. Several difficult aspects have to be overcome to obtain valid waveforms for problems where inductances contribute significantly. Mainly, the geometries are very complex and the interactions between the capacitive and inductive currents have to be… CONTINUE READING
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