Full-chip sub-threshold leakage power prediction model for sub-0.18 µm CMOS

@inproceedings{Narendra2002FullchipSL,
  title={Full-chip sub-threshold leakage power prediction model for sub-0.18 µm CMOS},
  author={Siva G. Narendra and Vivek De and Shekhar Y. Borkar and Dimitri Antoniadis and Anantha Chandrakasan},
  booktitle={ISLPED},
  year={2002}
}
The driving force for the semiconductor industry growth has been the elegant scaling nature of CMOS technology. In future CMOS technology generations, supply and threshold voltages will have to continually scale to sustain performance increase, control switching power dissipation, and maintain reliability. These continual scaling requirements on supply and threshold voltages pose several technology and circuit design challenges. With threshold voltage scaling sub-threshold leakage power is… CONTINUE READING
Highly Cited
This paper has 47 citations. REVIEW CITATIONS

Citations

Publications citing this paper.
Showing 1-10 of 33 extracted citations

Subthreshold leakage power distribution considering within-die and die-to-die P-T-V variations

Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758) • 2004
View 8 Excerpts
Highly Influenced

Leakage Models for High-Level Power Estimation

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems • 2018
View 1 Excerpt

Algorithms for CPU and DRAM DVFS under inefficiency constraints

2016 IEEE 34th International Conference on Computer Design (ICCD) • 2016
View 1 Excerpt

Hierarchical Statistical Leakage Analysis and Its Application

ACM Trans. Design Autom. Electr. Syst. • 2016
View 2 Excerpts

Similar Papers

Loading similar papers…