From software threads to parallel hardware in high-level synthesis for FPGAs

@article{Choi2013FromST,
  title={From software threads to parallel hardware in high-level synthesis for FPGAs},
  author={Jongsok Choi and S. Brown and J. Anderson},
  journal={2013 International Conference on Field-Programmable Technology (FPT)},
  year={2013},
  pages={270-277}
}
We describe the support within high-level hardware synthesis (HLS) for two standard software parallelization paradigms: Pthreads and OpenMP. [...] Key Method Essentially, our framework allows a software engineer to specify parallelism to an HLS tool using methodologies they are likely to be familiar with. An experimental study considers a variety of parallelization scenarios, including demonstrated speedups of up to 12.9× in circuit wall-clock time for the 16-thread case and area-delay product as low as 12% (~8…Expand
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