From signal temporal logic to FPGA monitors

@article{Jaksic2015FromST,
  title={From signal temporal logic to FPGA monitors},
  author={Stefan Jaksic and Ezio Bartocci and Radu Grosu and Reinhard Kloibhofer and Thang Nguyen and Dejan Nickovic},
  journal={2015 ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE)},
  year={2015},
  pages={218-227}
}
Due to the heterogeneity and complexity of systems-of-systems (SoS), their simulation is becoming very time consuming, expensive and hence impractical. As a result, design simulation is increasingly being complemented with more efficient design emulation. Runtime monitoring of emulated designs would provide a precious support in the verification activities of such complex systems. We propose novel algorithms for translating signal temporal logic (STL) assertions to hardware runtime monitors… CONTINUE READING

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