Fpga Technology Mapping Using Logic Blocks with Independent Luts

The logic blocks of a lookup table (LUT) based FPGA consist of one or more LUTs, possibly of diierent sizes. The problem of mapping a given combinational circuit to an FPGA with diierent sizes of LUTs, using as few of these logic blocks as possible, is an important and non-trivial extension of the traditional LUT based technology mapping problem. In this… CONTINUE READING