Formal verification of analog circuits in the presence of noise and process variation

  title={Formal verification of analog circuits in the presence of noise and process variation},
  author={R. Narayanan and Behzad Akbarpour and M. Zaki and S. Tahar and Lawrence Charles Paulson},
  journal={2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)},
We model and verify analog designs in the presence of noise and process variation using an automated theorem prover, MetiTarski. Due to the statistical nature of noise, we propose to use stochastic differential equations (SDE) to model the designs. We find a closed form solution for the SDEs, then integrate the device variation due to the 0.18¿m fabrication process and verify properties using MetiTarski. We illustrate the proposed approach on an inverting Op-Amp Integrator and a Band-Gap… Expand
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