Formal verification of an IBM CoreConnect processor local bus arbiter core

@inproceedings{Goel2000FormalVO,
  title={Formal verification of an IBM CoreConnect processor local bus arbiter core},
  author={Amit Goel and William R. Lee},
  booktitle={DAC},
  year={2000}
}
This paper describes the model checking effort for an arbiter core for the IBM CoreConnect Architecture. We present our verification methodology and describe how it was influenced by the architecture. We also present and analyze the bugs found and discuss the difficulties associated with verifying complex on-chip buses, highlighting the need for better tools and methodologies for their specification and verification. 
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Symbolic Model Checking: An Approach to the State Explosion Problem

  • K. L. McMillan
  • Technical Report CMU-CS-92-131, Carnegie Mellon…
  • 1992
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