Formal Verification of Combinational Circuit


W i t h the increase in the complexity of present day systems, proving the correctness of a design has become a major concern. Simulation based methodologies are general ly inadequate to validate the correctness of a design with a reasonable confidence. More and more designers are moving towards formal methods to guarantee the correctness of their designs… (More)
DOI: 10.1109/ICVD.1997.568079


7 Figures and Tables