• DOI:10.4204/EPTCS.327.1
• Corpus ID: 221995763

Formal Verification of Arithmetic RTL: Translating Verilog to C++ to ACL2

@inproceedings{Russinoff2020FormalVO,
  title={Formal Verification of Arithmetic RTL: Translating Verilog to C++ to ACL2},
  author={David M. Russinoff},
  booktitle={International Workshop on the ACL2 Theorem Prover and Its Applications},
  year={2020}
}

• David M. Russinoff
• Published in
  International Workshop on the…
  29 September 2020
• Computer Science

We present a methodology for formal verification of arithmetic RTL designs that combines sequential logic equivalence checking with interactive theorem proving. An intermediate model of a Verilog module is hand-coded in Restricted Algorithmic C (RAC), a primitive subset of C augmented by the integer and fixed-point register class templates of Algorithmic C. The model is designed to be as abstract and compact as possible, but sufficiently faithful to the RTL to allow efficient equivalence checking with a commercial tool. It is then automatically translated to the logic of ACL2, enabling a mechanically checked proof of correctness with respect to a formal architectural specification. In this paper, we describe the RAC language, the translation process, and some techniques that facilitate formal analysis of the resulting ACL2 code.