Formal Verification of Arithmetic RTL: Translating Verilog to C++ to ACL2

  title={Formal Verification of Arithmetic RTL: Translating Verilog to C++ to ACL2},
  author={David M. Russinoff},
  booktitle={International Workshop on the ACL2 Theorem Prover and Its Applications},
  • David M. Russinoff
  • Published in
    International Workshop on the…
    29 September 2020
  • Computer Science
We present a methodology for formal verification of arithmetic RTL designs that combines sequential logic equivalence checking with interactive theorem proving. An intermediate model of a Verilog module is hand-coded in Restricted Algorithmic C (RAC), a primitive subset of C augmented by the integer and fixed-point register class templates of Algorithmic C. The model is designed to be as abstract and compact as possible, but sufficiently faithful to the RTL to allow efficient equivalence… 

Figures from this paper

Properties of the Hebrew Calendar

We describe an ACL2 program that implements the Hebrew calendar and the formal verification of several of its properties, including the critical result that the algorithm that determines the placement



Formal Verification of Floating-Point RTL at AMD Using the ACL 2 Theorem Prover

The methodology is based on a mechanical translator from a synthesizable subset of the Verilog hardware description language to the formal logic of the ACL2 theorem prover, and its application to the floating-point units of commercial microprocessors produced by Advanced Micro Devices, Inc.

Use of Formal Verification at Centaur Technology

The formal methodology to verify components of a commercial 64-bit, x86-compatible microprocessor design at Centaur Technology, based on the ACL2 theorem prover, is described, which uses AIG- and BDD-based symbolic simulation and theorem proving techniques to show that the hardware models satisfy their specifications.

Experience with Embedding Hardware Description Languages in HOL

Three languages are being investigated: ELLA, Silage and VHDL and the approaches taken for these languages are compared and current progress on building semantically-based theorem-proving tools is discussed.

Modeling Algorithms in SystemC and ACL2

The formal language MASC is described, based on a subset of SystemC and intended for modeling algorithms to be implemented in hardware, by means of a special-purpose parser, which generates a SystemC variant that is suitable as input to a high-level synthesis tool.

Formal Verification of Floating-Point Hardware Design


  • Tao te Ching
  • 2016

const-fns-gen 'compare64 'r state) (DEFUNDD SGNA NIL (BITN (A) 63))

    Automatically generated definitions

    • Figure

    Put Me on the RAC

    • 2020

    B))) :HINTS (("Goal