Formal Verification of Architectural Power Intent

Abstract

This paper presents a verification framework that attempts to bridge the disconnect between high-level properties capturing the architectural power management strategy and the implementation of the power management control logic using low-level per-domain control signals. The novelty of the proposed framework is in demonstrating that the architectural power intent properties developed using high-level artifacts can be automatically translated into properties over low-level control sequences gleaned from UPF specifications of power domains, and that the resulting properties can be used to formally verify the global on-chip power management logic. The proposed translation uses a considerable amount of domain knowledge and is also not purely syntactic, because it requires formal extraction of timing information for the low-level control sequences. We present a tool, called POWER-TRUCTOR which enables the proposed framework, and several test cases of significant complexity to demonstrate the feasibility of the proposed framework.

DOI: 10.1109/TVLSI.2011.2180548

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Cite this paper

@article{Hazra2013FormalVO, title={Formal Verification of Architectural Power Intent}, author={Aritra Hazra and Sahil Goyal and Pallab Dasgupta and Ajit Pal}, journal={IEEE Trans. VLSI Syst.}, year={2013}, volume={21}, pages={78-91} }