Force-directed scheduling for Data Flow Graph mapping on Coarse-Grained Reconfigurable Architectures

@article{Fell2014ForcedirectedSF,
  title={Force-directed scheduling for Data Flow Graph mapping on Coarse-Grained Reconfigurable Architectures},
  author={Alexander Fell and Zolt{\'a}n Endre R{\'a}kossy and Anupam Chattopadhyay},
  journal={2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14)},
  year={2014},
  pages={1-8}
}
In terms of energy and flexibility, Coarse-Grained Reconfigurable Architectures (CGRA) are proven to be advantageous over fine-grained architectures, massively parallel GPUs and generic CPUs. However the key challenge of programmability is preventing wide-spread adoption. To exploit instruction level parallelism inherent to such architectures, optimal scheduling and mapping of algorithmic kernels is essential. Transforming an input algorithm in the form of a Data Flow Graph (DFG) into a CGRA… CONTINUE READING