Floorplanning and signal assignment for silicon interposer-based 3D ICs

Abstract

Interposer-based 3D ICs (or known as 2.5D ICs) have been seen as an alternative approach to true 3D stacked ICs, which mount multiple dies on a silicon interposer and route signals between dies by the interconnects in the interposer. However, the floorplan of dies on the interposer and the signal assignment for macro-bumps and TSVs will largely impact the wirelength of the interconnects in a 2.5D IC. Because long interconnects would degrade the performance of 2.5D ICs, the multi-die floorplanning problem and signal assignment problem for 2.5D ICs are critical. This paper presents an enumeration-based algorithm and a network-flow-based algorithm to solve the multi-die floorplanning and signal assignment problems in a 2.5D IC, respectively. Also, to speed up the floorplanning and signal assignment algorithms, several acceleration techniques are proposed. The experimental results reveal that this work can effectively reduce the total wirelength in a 2.5D IC and the acceleration techniques can significantly speed up the proposed algorithms.

DOI: 10.1145/2593069.2593142

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Cite this paper

@article{Liu2014FloorplanningAS, title={Floorplanning and signal assignment for silicon interposer-based 3D ICs}, author={Wen-Hao Liu and Min-Sheng Chang and Ting-Chi Wang}, journal={2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)}, year={2014}, pages={1-6} }