Floating-Point Matrix Multiplication in a Polymorphic Processor


We consider 64-bit floating-point matrix multiplication in the context of polymorphic processor architectures. Our proposal provides a complete and performance efficient solution of the matrix multiplication problem, including hardware design and software interface. We adopt previous ideas1, originally proposed for loosely coupled processors and message… (More)
DOI: 10.1109/FPT.2007.4439258


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