Floating-Point Divider Design for FPGAs

  title={Floating-Point Divider Design for FPGAs},
  author={Karl S. Hemmert and Keith D. Underwood},
  journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
Growth in floating-point applications for field-programmable gate arrays (FPGAs) has made it critical to optimize floating-point units for FPGA technology. The divider is of particular interest because the design space is large and divider usage in applications varies widely. Obtaining the right balance between clock speed, latency, throughput, and area in FPGAs can be challenging. The designs presented here cover a range of performance, throughput, and area constraints. On a Xilinx Virtex4-11… CONTINUE READING
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