Flip-flop chaining architecture for power-efficient scan during test application

@article{Gupta2005FlipflopCA,
  title={Flip-flop chaining architecture for power-efficient scan during test application},
  author={Shantanu Gupta and Tarang Vaish and Santanu Chattopadhyay},
  journal={14th Asian Test Symposium (ATS'05)},
  year={2005},
  pages={410-413}
}
Power dissipation in CMOS circuits during test time poses a crucial bottleneck for circuit performance and robustness. The power consumption due to switching activity while scan-in of test vectors and scan-out of responses is of particular concern. In this paper a methodology for scan chain modification and test vector adaptation is proposed to effectively reduce the scan test power consumption by controlling this switching activity. Proposed approach, unlike the many in published literature… CONTINUE READING