Flip-chip routing with unified area-I/O pad assignments for package-board co-design

@article{Fang2009FlipchipRW,
  title={Flip-chip routing with unified area-I/O pad assignments for package-board co-design},
  author={Jia-Wei Fang and Martin D. F. Wong and Yao-Wen Chang},
  journal={2009 46th ACM/IEEE Design Automation Conference},
  year={2009},
  pages={336-339}
}
In this paper, we present a novel flip-chip routing algorithm for package-board co-design. Unlike the previous works that can consider only either free- or pre-assignment routing, our router is the first work in the literature that can handle both the free-and pre-assignment routing. Based on the computational geometry techniques (e.g., the Delaunay triangulation and the Voronoi diagram), the router applies a unified network-flow formulation to perform congestion estimation for the pre… CONTINUE READING

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Key Quantitative Results

  • With the package and board co-design flow, we can achieve 100% routing completion.

Citations

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Redistribution layer routing for wafer-level integrated fan-out package-on-packages

  • 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
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  • 2013
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  • 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE)
  • 2012
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Escape Routing for Staggered-Pin-Array PCBs

  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Interface optimization for improved routability in chip-package-board co-design

  • International Workshop on System Level Interconnect Prediction
  • 2011
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Network Flows: Theory, Algorithms, and Applications

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