Flexible cache error protection using an ECC FIFO


We present ECC FIFO, a mechanism enabling two-tiered last-level cache error protection using an arbitrarily strong tier-2 code without increasing on-chip storage. Instead of adding redundant ECC information to each cache line, our ECC FIFO mechanism off-loads the extra information to off-chip DRAM. We augment each cache line with a tier-1 code, which provides error detection consuming limited resources. The redundancy required for strong protection is provided by a tier-2 code placed in off-chip memory. Because errors that require tier-2 correction are rare, the overhead of accessing DRAM is unimportant. We show how this method can save 15--25% and 10--17% of on-chip cache area and power respectively while minimally impacting performance, which decreases by 1% on average across a range of scientific and consumer benchmarks.

DOI: 10.1145/1654059.1654109
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@article{Yoon2009FlexibleCE, title={Flexible cache error protection using an ECC FIFO}, author={Doe Hyun Yoon and Mattan Erez}, journal={Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis}, year={2009}, pages={1-12} }