Flexibility of interconnection structures for field-programmable gate arrays

@article{Rose1991FlexibilityOI,
  title={Flexibility of interconnection structures for field-programmable gate arrays},
  author={J. Rose and S. Brown},
  journal={IEEE Journal of Solid-state Circuits},
  year={1991},
  volume={26},
  pages={277-282}
}
  • J. Rose, S. Brown
  • Published 1991
  • Engineering
  • IEEE Journal of Solid-state Circuits
The relationship between the routability of a field-programmable gate array (FPGA) and the flexibility of its interconnection structures is examined. The flexibility of an FPGA is determined by the number and distribution of switches used in the interconnection. While good routability can be obtained with a high flexibility, a large number of switches will result in poor performance and logical density because each switch has significant delay and area. The minimum number of switches required… Expand
255 Citations

Figures and Tables from this paper

FPGA routing structures : a novel switch block and depopulated interconnect matrix architectures
  • 33
  • PDF
Improving FPGA routing architectures using architecture and CAD interactions
  • 21
  • PDF
A detailed router for field-programmable gate arrays
  • 90
  • PDF
Memory/logic interconnect flexibility in FPGAs with large embedded memory arrays
  • 15
  • PDF
A stochastic model to predict the routability of field-programmable gate arrays
  • 69
  • PDF
Segmented Routing for Speed-Performance and Routability in Field-Programmable Gate Arrays
  • 29
  • PDF
Hierarchical interconnection structures for field programmable gate arrays
  • Y. Lai, P. Wang
  • Computer Science
  • IEEE Trans. Very Large Scale Integr. Syst.
  • 1997
  • 60
...
1
2
3
4
5
...

References

SHOWING 1-10 OF 23 REFERENCES
The effect of switch box flexibility on routability of field programmable gate arrays
  • J. Rose, S. Brown
  • Engineering
  • IEEE Proceedings of the Custom Integrated Circuits Conference
  • 1990
  • 30
A detailed router for field-programmable gate arrays
  • 130
  • PDF
The effect of logic block complexity on area of programmable gate arrays
  • 41
  • PDF
A 9000-gate user-programmable gate array
  • 50
An architecture for electrically configurable gate arrays
  • 82
  • PDF
An FPGA family optimized for high densities and reduced routing delay
  • 49
  • PDF
An efficient logic block interconnect architecture for user-reprogrammable gate array
  • 25
Segmented channel routing
  • 43
  • PDF
...
1
2
3
...