Fine-Grain Cell Design for Multiple-Valued Reconfigurable VLSI Using a Single Differential-Pair Circuit


This paper presents a fine-grain cell design for a Multiple-Valued (MV) reconfigurable VLSI using a single Differential-Pair Circuit (DPC). The VLSI involves a bitserial localized data transfer architecture. The cell consists of a Multiple-Valued Source-Coupled Logic (MVSCL)- based threshold logic gate, a dynamic latch and a switch block. The threshold… (More)
DOI: 10.1109/ISMVL.2006.22


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