FinFET scaling to 10 nm gate length

@article{Yu2002FinFETST,
  title={FinFET scaling to 10 nm gate length},
  author={Bin Cupertino Yu and Leland Chang and S. Ahmed and Haihong Fremont Wang and S. Bell and Chih-Yuh Yang and Cyrus Tabery and C. W. Ho and Qi San Jose Xiang and Tsu-Jae King and Jeffrey Bokor and Chenming Calvin Hu and Ming-Ren Cupertino Lin and David F. Kyser},
  journal={Digest. International Electron Devices Meeting,},
  year={2002},
  pages={251-254}
}
While the selection of new "backbone" device structure in the era of post-planar CMOS is open to a few candidates, FinFET and its variants show great potential in scalability and manufacturability for nanoscale CMOS. In this paper we report the design, fabrication, performance, and integration issues of double-gate FinFETs with the physical gate length being aggressively shrunk down to 10 nm and the fin width down to 12 nm. These MOSFETs are believed to be the smallest double-gate transistors… Expand

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