FinFET — A Self-Aligned Double-Gate MOSFET Scalable to 20 nm

  title={FinFET — A Self-Aligned Double-Gate MOSFET Scalable to 20 nm},
  author={Digh Hisamoto and Wonoh Lee and Jakub Kedzierski and Hideki Takeuchi and Kazuya Asano and Charles Kuo and Erik I. Anderson and Tsu-Jae King and Jeffrey Bokor and Chenming Calvin Hu},
MOSFETs with gate length down to 17 nm are reported. To suppress the short channel effect, a novel self-aligned double-gate MOSFET, FinFET, is proposed. By using boron-doped Si0 4Ge0 6 as a gate material, the desired threshold voltage was achieved for the ultrathin body device. The quasiplanar nature of this new variant of the vertical double-gate MOSFETs can be fabricated relatively easily using the conventional planar MOSFET process technologies. 

From This Paper

Figures, tables, and topics from this paper.


Publications citing this paper.

1,548 Citations

Citations per Year
Semantic Scholar estimates that this publication has 1,548 citations based on the available data.

See our FAQ for additional information.


Publications referenced by this paper.

Semiconductor thickness effects in the double-gate SOI MOSFET

  • B. Majkusiak, T. Janik, J. Walczak
  • IEEE Trans. Electron Devices , vol. 45, pp. 1127…
  • 1998
1 Excerpt

Design and performance considerations for sub-0.1 um double-gate SOI MOSFET’s

  • H. S. Wong, D. J. Frank, Y. Taur, J.M.C. Stork
  • IEDM Tech. Dig. , , pp. 747–750.
  • 1994

Metallized ultra-shallow-junction device technology for sub-0.1 um gate MOSFET’s

  • D. Hisamoto
  • IEEE Trans. Electron Devices , vol. 41, pp. 745…
  • 1994

A new scaling methodology for the 0.1–0.025 um MOSFET

  • C. Fiegna
  • inVLSI Symp. Tech. Dig. , , pp. 33–34.
  • 1993

Optimization of series resistance in sub-0.2 um SOI MOSFETs

  • L. T. Su, M. J. Sherony, H. Hu, J. E. Chung, D. A. Antoniadis
  • IEDM Tech. Dig. , , pp. 723–726.
  • 1993
1 Excerpt

Scaling theory for double-gate SOI MOSFET’s

  • K. Suzuki
  • IEEE Trans. Electron Devices , vol. 40, pp. 2326…
  • 1993

Monte carlo simulation of a 30 nm dual-gate MOSFET: How short can Si go

  • D. J. Frank, S. E. Laux, M. V. Fischetti
  • IEDM Tech. Dig., , pp. 553–556.
  • 1992
1 Excerpt

Novel polysilicon / TiN stacked - gate structure for fully - depleted SOI / CMOS

  • D. Hisamoto
  • IEDM Tech . Dig .
  • 1992

Similar Papers

Loading similar papers…