Field programmable gate arrays and floating point arithmetic

@article{Fagin1994FieldPG,
  title={Field programmable gate arrays and floating point arithmetic},
  author={Barry S. Fagin and C. Renard},
  journal={IEEE Trans. Very Large Scale Integr. Syst.},
  year={1994},
  volume={2},
  pages={365-367}
}
  • B. Fagin, C. Renard
  • Published 1 September 1994
  • Computer Science
  • IEEE Trans. Very Large Scale Integr. Syst.
We present empirical results describing the implementation of an IEEE Standard 754 compliant floating-point adder/multiplier using field programmable gate arrays. The use of FPGA's permits fast and accurate quantitative evaluation of a variety of circuit design tradeoffs for addition and multiplication. PPGA's also permit accurate assessments of the area and time costs associated with various features of the IEEE floating-point standard, including rounding and gradual underflow. These costs are… 
Parameterised floating-point arithmetic on FPGAs
  • A. Jaenicke, W. Luk
  • Computer Science
    2001 IEEE International Conference on Acoustics, Speech, and Signal Processing. Proceedings (Cat. No.01CH37221)
  • 2001
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A method, based on the Handel-C language, for producing technology-independent pipelined designs that allow compile-time parameterisation of design precision and range, and optional inclusion of features such as overflow protection, gradual underflow and rounding modes of the IEEE floating-point format is developed.
FPGA Based 32-Bit Floating Point Arithmetic Unit for Floating Point Processors
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A 32 bit floating point arithmetic unit with IEEE 754 Standard has been designed using VHDL code and all operations of addition, subtraction, multiplication and division are tested on Xilinx.
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This paper implements an efficient 32bit floating point adder according to ieee 754 standard with optimal chip area and high performance using VHDL using Xilinx ISE Simulator.
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The implementation of IEEE single precision floating-point multiplication and addition is discussed, followed by a discussion of an algorithm, matrix multiplication, based on these operations, which achieves performance comparable to conventional microprocessors.
FPGA Based 32-Bit Floating Point Arithmetic Unit for Floating Point Processors
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A 32 bit floating point arithmetic unit with IEEE 754 Standard has been designed using VHDL code and all operations of addition, subtraction, multiplication and division are tested on Xilinx.
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A high speed floating point double precision adder/subtractor and multiplier are implemented on a Virtex-6 FPGA and are compliant with IEEE-754 format.
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A parameterizable floating-point library for arithmetic operators based on FPGAs was implemented and a tradeoff analysis of the hardware implementation was performed, which enables the designer to choose the suitable bit-width representation and error associated, as well as the area cost, elapsed time and power consumption for each arithmetic operator.
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References

Computer Architecture: A Quantitative Approach
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