Field programmable gate arrays and floating point arithmetic

@article{Fagin1994FieldPG,
  title={Field programmable gate arrays and floating point arithmetic},
  author={B. Fagin and C. Renard},
  journal={IEEE Trans. Very Large Scale Integr. Syst.},
  year={1994},
  volume={2},
  pages={365-367}
}
  • B. Fagin, C. Renard
  • Published 1994
  • Computer Science
  • IEEE Trans. Very Large Scale Integr. Syst.
We present empirical results describing the implementation of an IEEE Standard 754 compliant floating-point adder/multiplier using field programmable gate arrays. The use of FPGA's permits fast and accurate quantitative evaluation of a variety of circuit design tradeoffs for addition and multiplication. PPGA's also permit accurate assessments of the area and time costs associated with various features of the IEEE floating-point standard, including rounding and gradual underflow. These costs are… Expand
Parameterised floating-point arithmetic on FPGAs
  • A. Jaenicke, W. Luk
  • Computer Science
  • 2001 IEEE International Conference on Acoustics, Speech, and Signal Processing. Proceedings (Cat. No.01CH37221)
  • 2001
A re-evaluation of the practicality of floating-point operations on FPGAs
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