Field-Programmable Gate-Array ( FPGA ) Implementation of Low-Density Parity-Check ( LDPC ) Decoder in Digital Video Broadcasting – Second Generation Satellite ( DVB-S 2 )

@inproceedings{Chi2010FieldProgrammableG,
  title={Field-Programmable Gate-Array ( FPGA ) Implementation of Low-Density Parity-Check ( LDPC ) Decoder in Digital Video Broadcasting – Second Generation Satellite ( DVB-S 2 )},
  author={Kung Chi and Cinnati Loi},
  year={2010}
}
In recent years, LDPC codes are gaining a lot of attention among researchers. Its nearShannon performance combined with its highly parallel architecture and lesser complexity compared to Turbo-codes has made LDPC codes one of the most popular forward error correction (FEC) codes in most of the recently ratified wireless communication standards. This thesis… CONTINUE READING