Field-Based Capacitance Modeling for Sub-65-nm On-Chip Interconnect

@article{Zhao2009FieldBasedCM,
  title={Field-Based Capacitance Modeling for Sub-65-nm On-Chip Interconnect},
  author={Wei Zhao and Xia Li and Sam Guoping Gu and S. Kang and M. Nowak and Yu Cao},
  journal={IEEE Transactions on Electron Devices},
  year={2009},
  volume={56},
  pages={1862-1872}
}
Back-end-of-the-line (BEOL) interconnect becomes a limiting factor to circuit performance in scaled complementary metal-oxide-semiconductor design. To accurately extract its paratactic capacitance for circuit simulation, compact models should be scalable with wire geometries and should capture the latest technology advances, such as the air gap and Cu diffusion barrier. This paper achieves these goals based on the distribution of the electric field in on-chip BEOL structures. By decomposing the… CONTINUE READING
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