Feasibility exploration of NVM based I-cache through MSHR enhancements

  title={Feasibility exploration of NVM based I-cache through MSHR enhancements},
  author={Manu Perumkunnil Komalan and Jos{\'e} Ignacio G{\'o}mez P{\'e}rez and Christian Tenllado and Praveen Raghavan and Matthias Hartmann and Francky Catthoor},
  journal={2014 Design, Automation & Test in Europe Conference & Exhibition (DATE)},
SRAM based memory systems are plagued by a number of problems like sub-threshold leakage and susceptibility to read/write failure with dynamic voltage scaling schemes or low supply voltage. Non-Volatile Memory (NVM) technologies are being explored extensively nowadays to replace the conventional SRAM memories even for level 1 (L1) caches. These NVMs like Spin Torque Transfer RAM (STT-MRAM), Resistive-RAM (ReRAM) and Phase Change RAM (PRAM) are less hindered by leakage problems with technology… CONTINUE READING

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Key Quantitative Results

  • According to our simulations, appropriate tuning of selective architecture parameters can reduce the performance penalty introduced by the NVM (~45%) to extremely tolerable levels (~1%) and show energy gains up to 35%.


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