Fault-tolerance and two-level pipelining in VLSI systolic arrays

  title={Fault-tolerance and two-level pipelining in VLSI systolic arrays},
  author={H. T. Kung and Monica S. Lam},
This paper addresses two important issues in systolic array designs: fault-tolerance and two-level pipelining. The proposed "systolic" fault-tolerant scheme maintains the original data flow pattern by bypassing defective cells with a few registers. As a result, many of the desirable properties of systolic arrays (such as local and regular communication between cells) are preserved. Two-level pipelining refers to the use of pipelined functional units in the implementation of systolic cells. This… CONTINUE READING