Fault modeling in controllable polarity silicon nanowire circuits

  title={Fault modeling in controllable polarity silicon nanowire circuits},
  author={Hassan Ghasemzadeh and Pierre-Emmanuel Gaillardon and Giovanni De Micheli},
  journal={2015 Design, Automation & Test in Europe Conference & Exhibition (DATE)},
Controllable polarity silicon nanowire transistors are among the promising candidates to replace current CMOS in the near future owing to their superior electrostatic characteristics and advanced functionalities. From a circuit testing point of view, it is unclear if the current CMOS and Fin-FET fault models are comprehensive enough to model all defects of controllable polarity nanowires. In this paper, we deal with the above problem using inductive fault analysis on three-independent-gate… CONTINUE READING
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